1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device, in which method a mold is used to resin encapsulate a semiconductor element and a tape carrier by a method such as a low-pressure transfer.
2. Description of the Related Art
FIG. 8 is a perspective view partially in section of a conventional resin-sealed type semiconductor device. It shows how a low-pressure transfer method resin-molds a semiconductor element connected by wire bonding.
In the drawing, numeral 1 denotes the core of a semiconductor device or a semiconductor element, usually referred to as an IC chip. Electronic circuitry is finely and delicately formed on the IC chip 1 on a semiconductor substrate, made of, for example, silicon. Numeral 2 denotes a die bonding pad where the IC chip 1 is mounted. Numeral 3 denotes leads, each composed of an inner lead electrically connected to an electrode on the IC chip 1 and of an outer lead electrically connected to an external device and the substrate. Numeral 4 denotes wires electrically connecting the IC chip 1 to the leads 3, and numeral 5 denotes a sealing resin which encapsulates the IC chip 1 to protect it from external surroundings and force.
A so-called Tape Automated Bonding (TAB) method using a tape carrier is employed in place of the above wire bonding method which has been widely used as a technique for connecting the electrodes on an IC chip (a semiconductor element) 1. The TAB method will be briefly described with reference to FIGS. 9a, 9b, 10a and 10b. In the drawings, numeral 6 designates a tape, serving as a base material of the tape carrier, which is made of a flexible insulating material, such as polyimide, and has a film-like configuration. As described below, three types of holes 7-9 are formed in the tape 6. The hole 7 is a center device hole at the center of the width of the tape 6, and is situated in a position where the IC chip 1, described later, is installed. The holes 8 are sprocket holes at fixed intervals on both sides of the tape 6 in the width direction of the tape 6. The sprocket holes 8 are used for roughly positioning the tape 6 and the IC chip 1 when they are bonded together. The holes 9 are a plurality of outer-lead holes surrounding the center device hole 7. The outer-lead holes 9 are used when the outer leads are bonded as described later, and are separated by bridges 10 formed in positions corresponding to the four corners of the center device hole 7. Numeral 11 designates a plurality of lead patterns, made of an electrically conductive material, formed in predetermined positions on the obverse surface of the tape 6. Each lead pattern is composed of an inner lead 11a facing the center device hole 7, and an outer lead 11b extending over the outer-lead hole 9 and toward the outside. Numeral 11c designates test pads for examining whether the IC chip 1 is defective or whether the connection between the inner leads 11a and the IC chip 1 is defective after the inner leads have been bonded. Numeral 12 designates a lead support portion supporting the lead patterns 11, and 13 designates bumps usually formed on the obverse surface of the IC chip 1. The bumps 13 are interposed between the IC chip 1 and the inner leads 11a.
A description will be given of a method for installing the IC chip 1 in the thus-constructed carrier tape 6.
As shown in FIG. 10a, first, the IC chip 1 is placed in the center device hole 7 in the tape 6. The IC chip 1 or the tape 6 is positioned so that the bumps 13 on the IC chip 1 can face predetermined locations of the inner leads 11a. Next, the bumps 13 on the IC chip 1 are connected to the inner leads 11a by a thermocompression bonding method. This forms the tape carrier in which the IC chip 1 installed. FIG. 10b shows an example of such a tape carrier.
A method using a liquid resin for sealing the tape carrier will be described with reference to FIGS. 11a and 11b. In the drawings, numeral 14a indicates the liquid resin before it sets; 14b, the liquid resin after it has set; and 15, a syringe for dropping the liquid resin 14a. First, the liquid resin 14a is dropped onto the tape carrier shown in FIG. 11a, and then it is heated and thereby set to encapsulate the tape carrier, as illustrated in FIG. 11b.
The construction of the conventional semiconductor device and the manufacturing method employed therefor are as described above. Because of the following problems, there is a limit of 1.0 mm in making semiconductor devices thinner.
A comparison between the wire bonding and TAB methods will be explained first. FIGS. 12a and 12b are enlarged cross-sectional views illustrating the thicknesses of resin encapsulating IC chips in accordance with the wire-bonding method and the TAB method, respectively. In FIG. 12a, reference character A indicates the height of the wire 4 in accordance with the wire bonding method. The height A is usually 180 .mu.m, and at least approximately 150 .mu.m. Reference character B indicates the thickness of the sealing resin 5 provided for protecting the wire 4 and the electronic circuitry on the surface of the IC chip 1 from external contamination or moisture. In FIG. 12b, reference character C indicates the height of the bump 13 on the IC chip 1 which is usually about 25 .mu.m. Reference character D indicates the thickness of the inner lead 11a (metal foil made of copper or the like) which is usually 35 .mu.m.
It is obvious from the above measurements that when the thickness of the resin used in the wire bonding method is compared with that in the TAB method, the resin used in the TAB method can be made thinner by an amount equal to a thickness A-C-D. Usually, this resin is approximately 120 .mu.m thick. Thus the TAB method is advantageous when thin semiconductor devices are manufactured, and, in fact, has hitherto been employed for manufacturing such devices.
As shown in FIGS. 11a and 11b, the liquid resin 14a seals the tape carrier in the conventional TAB method. It is known that this liquid resin 14a is generally less reliable than sealing resins used in the low-pressure transfer method. A pressure cooker test (PCT) is conducted at high temperature and under high pressure using liquid resin R1 and transfer mold resins R2 and R3. Table 1 shows the results of the PCT.
TABLE 1 ______________________________________ Amounts of PCT time required until reject rates reach the following values Classifi- Reject Reject Reject Resins cation rate 10% rate 50% rate 90% ______________________________________ R1 Liquid 24 hours 48 hours 56 hours resin R2 Transfer 580 hours 1400 hours 2000 hours mold resin R3 Transfer 610 hours 1800 hours 2800 hours mold resin ______________________________________
Table 1 lists the amounts of test time (PCT time) required for the reject rates to reach 10%, 50% and 90%. It is understood that the reliability of the liquid resin R1 is approximately 1/10 to 1/20 that of the transfer mold resins R2 and R3.
We have tried to adapt the low-pressure transfer method to the TAB method, and have applied for patents (refer to Japanese Patent Publications Nos. 1-198041 and 1-155635). Apparently, the following five items are required for decreasing the thickness of a semiconductor device.
1) reduction of the amount each inner lead 11a droops PA1 2) limitation of the variation of the inner lead droop PA1 3) reduction, as much as possible, of the minimum melt viscosity of sealing resin PA1 4) limitation of the amount a mold clamps the lead support portion 12 of the carrier tape PA1 5) formation of a hole in the lead support portion 12 so that variations in the amount of resin pouring from above and under the lead portion 12 are limited.
We have already applied for patents regarding the fifth item (refer to Japanese Patent Publications Nos. 1-238031, 1-120835 and 1-244629).
The first, second and third items will be explained. FIG. 13a is a view used for illustrating the first item when a thin semiconductor device is manufactured. The low-pressure transfer method, using the TAB method, resin-seals the thin semiconductor device. When the carrier tape 6 and the IC chip 1 are bonded together according to the conventional TAB method, the amount E each inner lead 11a droops is not accurately controlled; consequently, drooping exceeding 100 .mu.m is tolerable. Thus the thickness F of resin on the IC chip 1 will be thicker, by 100 .mu.m or more, than the thickness (B+C+D) of the resin shown in FIG. 12b. In the low-pressure transfer method, the thickness of the resin on the IC chip 1 is basically the same as that of the resin beneath the IC chip 1. For this reason, the semiconductor device will be thicker than necessary and two times as thick as the amount E each inner lead 11a droops.
FIGS. 14a through 14c are views illustrating the above second and third items when a thin semiconductor device is manufactured. The thin semiconductor device is resin-sealed by the low-pressure transfer method using the TAB method. In the conventional TAB method, not only the amount E each inner lead 11a droops, but also a variation in the amounts all the inner leads 11a droop, is controlled. When this variation is not controlled, when molds 16a and 16b are designed on the basis of the measurements shown in FIG. 13b, showing a state in which each inner lead 11a does not droop, and when each inner lead 11a actually droops with a variation G, as shown in FIG. 14a, the thickness H of the resin on the IC chip 1 will increase from the standard thickness (B+C+D) by an amount equal to the variation G, and will become a total thickness (B+C+D+G).
On the other hand, the thickness J of the resin beneath the IC chip 1 will decrease from the standard thickness (B+C+D) by an amount equal to the variation G, and will be a total thickness (B+C+D-G). In the end, a difference between the thickness of the resin on the IC chip 1 and that of the resin beneath the IC chip 1 is twice the amount of the variation G. Since the thickness H of the thin semiconductor device is approximately 200 .mu.m or less, if the variation G becomes as great as 50 .mu.m, then the thickness H becomes approximately 250 .mu.m, and the thickness J becomes approximately 150 .mu.m. Thus the difference in thicknesses of the resins on and beneath the IC chip 1 becomes greater. For this reason, when the resin is introduced by the low-pressure transfer method, as shown in FIG. 14b, there will be a considerable difference in the amount the resin flows. As shown in FIG. 14b, because of this difference, the IC chip 1 is moved in a slight rotative manner in the direction indicated by arrow K. As the result, as depicted in FIG. 14c, a resin path beneath the IC chip 1 becomes extremely narrow, thus causing the resin to set while the resin is flowing and thus forming a void 17 beneath the IC chip 1. In an extreme case, there is a risk that the IC chip 1 will be exposed.
The amounts the inner leads 11a droop are examined so that not only the void 17 is prevented from being formed, but also the reverse surface of the chip 1 is prevented from being exposed. The formation of the void 17 and the exposure of the chip 1 are caused by the variation in the amounts the inner leads 11a droop. The result of this examination shows that when the variation is limited to 30 .mu.m or less, the above problems will not occur. The viscosity of the sealing resin is also examined so that it is sufficient for preventing the IC chip 1 from being moved in a slight rotative manner when the inner leads 11a droop, as shown in FIG. 14b. The result of this examination indicates that when the minimum melt viscosity is limited to 200 P or less, the IC chip 1 will not be moved in a slight rotative manner.